The present invention relates to a semiconductor memory device and to a method for driving the semiconductor memory device. More particularly, the invention relates to stably providing a clock at the memory device at a predetermined timing after a power down mode.
Generally, semiconductor memory devices such as a double data rate synchronous DRAM (DDR SDRAM) receive external clock signals to generate internal clock signals. A number of circuits in such semiconductor memory devices receive the internal clock signals for use as reference clocks of corresponding circuits. A clock skew may occur in a semiconductor memory device due to a delay generated by a transmission route for transmitting the internal clock in the semiconductor memory device. Thus, the semiconductor memory device includes a clock synchronization circuit to compensate the clock skew. A phase locked loop (PLL) and a delay locked loop (DLL) represent the clock synchronization circuit.
The semiconductor memory device receives an external power voltage to generate internal power voltages. The internal power voltages operate at various voltage levels. For example, the internal power voltages include a pumping power voltage that is supplied to word lines and higher than the external power voltage, a core power voltage supplied to a bit line sense amp amplifier, a peripheral circuit power voltage supplied to a peripheral circuit, and a DLL power voltage supplied to a DLL.
The semiconductor memory devices have been developed to meet requirements for very large scale integration, high-speed, and low power. Generally, a power down mode is used for low power consumption. The power down mode indicates an operation mode for minimizing current consumption in the semiconductor memory device. When the semiconductor memory device enters the power down mode, it consumes minimum current.
FIG. 1 is a block diagram of a typical DLL.
Referring to FIG. 1, the DLL includes a phase detecting unit 110, a control signal generating unit 130, a variable delaying unit 150, and a delay replicating unit 170.
The phase detecting unit 110 detects phases of an external clock signal CLK_EXT and a feedback clock signal CLK_FED to output a detect signal DET. The control signal generating unit 130 generates a corresponding delay control signal CNT_D in response to the detect signal DET. The variable delaying unit 150 delays the external clock signal CLK_EXT in response to the delay control signal CNT_D to generate a DLL clock signal CLK_DLL. The delay replicating unit 170 delays the DLL clock signal CLK_DLL for a time caused by a clock path through which the external clock signal CLK_EXT is transmitted to a data output circuit to generate a feedback clock signal CLK_FED.
The variable delaying unit 150 includes a plurality of unit delay cells (not shown). The variable delaying unit 150 receives an operation voltage from a DLL power voltage V_DLL.
FIG. 2 is a timing diagram showing a locking operation of the DLL in FIG. 1. For the convenience of explanation, it is assumed that the cycle of an external clock signal CLK_EXT is 10 ns and a phase difference between the locked DLL clock signal CLK_DLL and the external clock signal CLK_EXT is 2 n. It is assumed that each of the unit delaying cell delays an input signal for 70 ps and the variable delaying unit 150 is set to delay the external clock signal CLK_EXT for 1 ns at an initial operation time. An initial delay time of the external clock signal CLK_EXT is 1 ns.
Referring to FIGS. 1 and 2, the phase detecting unit 110 compares the external clock signal CLK_EXT with the feedback clock signal CLK_FED to output the detect signal DET. Then, the control signal generating unit 130 generates a delay control signal CNT_D according to the detect signal DET. The variable delaying unit 150 changes the number of activated unit delay cells in response to the delay control signal CNT_D.
When hundred unit delay cells in the variable delaying unit 150 are activated, the variable delaying unit 150 delays the external clock signal CLK_EXT for 8 ns.
When the variable delaying unit 150 delays 8 ns, a phase difference between the DLL clock signal CLK_DLL and the external cock signal CLK_EXT becomes 2 ns. In this case, the feedback clock signal CLK_FED from the delay replicating unit 170 is synchronized with the external clock signal CLK_EXT. This state is called that the DLL clock signal CLK_DLL is locked.
A normal mode is described, hereinbefore. The semiconductor memory device enters the power down mode after a normal mode.
Hereinafter, the power down mode is described in detail. When the semiconductor memory device enters the power down mode, the DLL stores locking information and stops the locking operation. When the semiconductor memory device leaves the power down mode, the variable delaying unit 150 starts to operate with the locking information stored before entering the power down mode. The DLL power voltage V_DLL supplied to the variable delaying unit 150 may drop due to an immediate circuit operation. Because the power voltage should be provided to all circuits in the memory device when the semiconductor memory device escapes the power down mode.
FIG. 3 is a timing diagram showing a problem occurring after leaving the power down mode.
Referring to FIGS. 1 to 3, the DLL clock signal CLK_DLL is locked totally to be delayed for 8 ns in the locking state. In detail, the DLL clock signal CLK_DLL is set to be initially delayed for 1 ns and then delayed for 7 ns by hundred unit delay cells of the variable delaying unit 150.
When the semiconductor memory device escapes the power down mode, since the power voltage is supplied to lots of circuit blocks in the memory device, the power voltage V_DLL temporally drops. Thus, delay time of the unit delay cells in the variable delaying unit 150 increases. That is, when the variable delaying unit 150 is locked for 8 ns by hundred unit delay cells before entering the power down mode, the delay time of the variable delaying unit 150 temporally increases when the semiconductor memory device escapes the power down mode. The delay time in hundred unit delay cells increases due to the voltage drop of the power voltage V_DLL. That means that the DLL clock signal CLK_DLL is delayed for delay time of 8 n+a.
Because of that, a DQS signal, i.e., a reference signal for outputting data, generated by the DLL clock signal CLK_DLL does not have a predetermined timing in comparison with the external clock signal CLK_EXT. A tDQSCK, i.e., a margin timing which is a specification between the external clock signal CLK_EXT and the DQS signal, is not satisfied. The more unit delay cells are used before entering the power down mode, the more difficult it becomes to be satisfied with the tDQSCK.